Rambus is a premier chip and silicon IP provider making data faster and safer. They are seeking a Design Verification Engineer Intern to work with their Memory Interface Chip team, focusing on developing verification environments and debugging functional issues.
Responsibilities
Understand the architecture of the chip and functional blocks.
Develop/maintain verification environments for chip level verification and enhance/use the automated regression infrastructures.
Create testplan and develop test cases/sequences in UVM.
Debug functional issues in the DUT based on the good understanding of the architectural specification.
Closely work with Design/Architecture/Circuit team to identify and align with the Milestones and Quality metrics of the project.
Qualification
Required
Major in EE, CS or related.
Proficient in Verilog, systemverilog and UVM.
Familiar with Linux environment and the industry’s prevailing EDA tools.
Have better understanding of Verification methodology and concepts.
Have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release.
Have excellent communication skills (both written and oral) and cross-team/function collaboration capability.
Experienced in code coverage and functional coverage closure.
Strong problem-solving skills.
Preferred
Benefits
Rambus designs, develops and licenses chip interface technologies and architectures that are used in digital electronics products.
