Marvell Technology provides semiconductor solutions that support enterprise, cloud, AI, and carrier data infrastructure. The Design-for-Test Intern will help design and implement DFT designs and reference flows for system-on-chip designs, while supporting verification, debugging, CAD flow improvements, and successful customer delivery.
Responsibilities
Understand the design requirements and customer specifications
Learn and run the defined computer-aided design (CAD) tools/flow for the assigned designs
Design and develop the SOC using Linux, TCL, Python/Perl (or other equivalent scripting languages)
Analyze, debug, and implement DFT features using defined CAD tools/flow
Collaborate with global CAD teams on design flow fixes and feature improvements
Assist in design verification efforts using ICL/PDL constructs and SV/UVM
Qualification
Required
Currently enrolled in a Bachelor's Degree in EE, CE, or a related field with an expected graduation date of Fall 2027 – Summer 2028
Language Fluency – Fluent in English Language – written & verbal
Preferred
Basic understanding of Linux/Unix/BSD Internals, with experience working on multi-threaded systems
Strong programming skills in scripting languages (e.g., TCL, Python) in a Unix type environment, with good problem-solving skills
Knowledge of SOC (system on a chip) design flow and DFT practices is a plus, e.g., At-Speed Test, Built-in Self-Test (BIST), Automated Test Pattern Generation (ATPG), IEEE1149.6 (AC-JTAG), and IEEE1687 (IJTAG)
Benefits
Eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers.
Medical, dental, and vision coverage for interns.
Perks and discounts.
Robust mental health resources to prioritize emotional well-being.
Paid holidays.
Additional compensation may be available for intern PhD candidates.
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