Design for Test Engineering Intern - Bachelors Degree
Westborough, MA
Internship
Onsite
$28/hr - $55/hr
Intern
Marvell Technology is a leader in semiconductor solutions that power data infrastructure across various domains. The Design for Test Engineering Intern will work with a high-performing DFT/DV team, focusing on design verification and ATE pattern development using Siemens EDA tools.
Responsibilities
UVM test case development when new DFT RTL is added into a design.
Opportunities for script development where technical details of the underlying DFT architecture are abstracted into control files which then allow developing design verification flows that can span a generation of designs.
Opportunity to work with JTAG, 1687, end evolving chiplet to chiplet test busses.
Use of 1687 ICL/PDL to automate the creation of functional test patterns deployed on ATE.
Debug of high speed IOs to include DDR and SERDES, collaborating with designers, internal and third-party IP developers, to understand test requirements, help architect test access, verify the proper integration in the netlist, develop patterns, and support ATE bring-up and debug.
Use of Siemens EDA tools to insert scan and memory BIST, and the verification of these inserted test elements.
Qualification
Required
Working towards a Bachelor’s degree in Computer Science, Electrical Engineering or related fields
Preferred
VLSI/SCAN/ATPG and UVM/Verification coursework preferred
Desire to work with scan/ATPG, memory BIST, using Siemens tools
Desire to work with System Verilog, UVM, Verification Test Plans, Coverage Driven Verification, Code Coverage, verification environments, test case simulation and debug.
Benefits
Medical, dental and vision coverage
Perks and discount programs
Wellness & mental health support including coaching and therapy
Paid holidays
Paid volunteer days
Paid sick time
We believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology.
